1. Field of the Invention
This invention relates to digital computer memory storage and specifically to digital random access memory cells employing complementary field effect transistors.
2. Description of the Prior Art
The present invention includes a random access memory cell. Random access memory cells are of two basic types, static and dynamic. The present invention includes a static type of random access memory cell.
Random access memory cells in the prior art resemble the type of memory cell shown in the schematic in FIG. 1. The RAM cell in FIG. 1 contains the DATA line 1 and a DATA- line 12. DATA and DATA- are input to the RAM cell as shown when the WORD ADDRESS line 11 is active. The WORD ADDRESS line 11 actuates the transistors 5 and 6 to place data in the data latch. The data latch consists of transistors 1, 2, 3 and 4 that are connected to transistors 5 and 6 and are cross connected together. Transistors 1 and 2 are n-channel devices and transistors 3 and 4 are p-channel devices. When a 1 is to be written into the RAM cell, the RAM cell DATA line 1 is high and DATA- line 12 is low, the 0 from the DATA- line 12 will be coupled onto node 7 through transistor 6, overriding the "1" being held on node 8 by transistor 3; the 0 at node 7 will activate the p-channel transistor 4 and inactivate the n-channel transistor 2, forcing a 1 on nodes 9 and 10 which enables transistor 1 and reinforces the 0 on node 7 and 8. Therefore, the 0 that exists or the charge that exists in node 8 will be the same at node 7 and likewise, the charge that exists at node 10 will be the same at node 9. Therefore data has been written into the RAM cell. However, problems occur when new data is to be written into the RAM cell that alters the state of the device. If the threshold characteristics of both the n-channel and p-channel devices is about the same, then transistors 5 and 6 must have channels that are considerably wider than transistors 3 and 4 to eliminate the resistance in changing or altering the state of the data stored in the latch. In other words, data from DATA lines 1 and DATA- line 12 must overwrite the data that already exists in memory. As the design voltage for the CMOS RAM cells becomes smaller, this difference in size between the driving transistors 5 and 6 and the latch transistors 3 and 4 becomes greater. Drive transistors 5 and 6 must be increased to size to offset the voltage differential required to overwrite the data in the RAM cell. Therefore, as this design voltage decreases, the actual size of the RAM cell must increase in proportion to the remaining number of devices. This increase in RAM cell size is not desirable.
The object of the present invention is to provide a RAM cell that allows new data to be written into the cell altering the state of the cell at lower design voltages and smaller RAM cell sizes.